1. Field of the Invention
The present invention relates to an amplifying type solid-state imaging apparatus in which amplifying type solid-state imaging devices are arranged in a matrix configuration, each of the amplifying type solid-state imaging devices amplifying a signal within a pixel by a transistor such as an MOS (Metal-Oxide-Semiconductor) FET (Field Effect Transistor) or a junction gate type FET.
2. Description of the Related Art
In order to replace a charge-coupled device (CCD) which is currently in wide use in a solid-state imaging apparatus, an amplifying type solid-state imaging apparatus is proposed. The amplifying type solid-state imaging apparatus does not read out a signal charge generated in a pixel as it is but amplifies it within the pixel, and then successively reads out the amplified signal charge by a scanning circuit. By amplifying the signal charge within the pixel, an amount of signals is sufficiently secured. Moreover, the limitation of an amount of signals in connection with the read-out is eliminated, and a dynamic range becomes better for the amplifying type device than for the CCD. Furthermore, it is sufficient to drive only the horizontal and vertical lines and the selection switch, which include pixels from which the signal is to be read out. As a result, the amplifying type solid-state imaging device is characterized with lower driving voltage and less power consumption than the CCD.
Transistors are typically used for amplifying a signal within each pixel. Depending on the type of transistors used, the amplifying type solid-state imaging device is categorized into an SIT type, a bipolar type, an FET type (MOS type or junction type), etc. In the SIT type and bipolar type devices, the scanning circuit for reading out the signal charge typically has a transistor structure constructed in the depth-direction. Since the MOS-FET type device has a transistor structure constructed parallel to the substrate surface, the MOS-FET type device has a simpler structure and can be readily produced. Therefore, it is structurally advantageous to employ the FET type device to a pixel when the overall structure of the apparatus is under consideration. Furthermore, the FET type device where the pixel includes a single FET is advantageous in increasing the pixel density. Reported as this type are a CMD (Charge Modulation Device) type, an FGA (Floating Gate Array) type, a BCM (Bulk Charge Modulated Device) type, etc.
FIGS. 1A and 1B illustrate a pixel of a conventional CMD type amplifying type solid-state imaging apparatus. FIG. 1A is a plan view of the pixel, and FIG. 1B is a cross-sectional view of the pixel taken along the G--G line in FIG. 1A. The CMD type pixel structure shown in FIGS. 1A and 1B is reported, for example, in "Gate accumulating type MOS phototransistor image sensor" by Nakamura et al., 1986 National Convention of the Institute of Television Engineers of Japan, page 57.
As illustrated in FIG. 1B, an n-type well 2 is formed on a p-type substrate 1 as a buried channel, and a gate electrode 4 is formed on the n-type well 2 with an insulating film 3 being inserted therebetween. A source region 5 and a drain region 6 which are made of a high concentration n.sup.+ -type layer and are separated from each other are also formed to the surface side of the n-type well 2.
As illustrated in FIG. 1A, the gate electrode 4 of each of the pixels arranged in the horizontal direction are all connected to a gate terminal 7, and the source region 5 of each of the pixels arranged in the vertical direction are all connected to a source terminal 8. Furthermore, each drain region 6 connects pixels in a mesh-like manner, and this drain region 6 is connected to a drain terminal 9. A plurality of such pixels are arranged both in the horizontal and vertical directions so as to form a matrix, thereby constituting a CMD type pixel unit.
Hereinafter, the operation of the CMD type pixel unit whose structure is described above will be described.
FIG. 2 shows the potential distribution in the depth-direction taken along the H--H line in FIG. 1B. As illustrated in FIG. 2, a voltage V.sub.L is applied as a gate voltage to the respective gate electrodes 4 of pixels arranged in the horizontal direction via the corresponding gate terminal 7, and a signal charge (positive holes) generated by photoelectric conversion in each pixel arranged in the horizontal direction is accumulated at the interface of the semiconductor and the insulator 3. Next, when reading out the signal, the gate voltage applied to the gate electrodes 4 is changed to a voltage V.sub.M which is higher than the voltage V.sub.L. When this is being done, the current flowing between the drain region 6 and the source region 5 of the transistor changes depending on the amount of accumulated signal charge. This changed current is to be read out as a signal output through the source terminal 8. When the changed current is being read out, since the gate voltage applied to other pixels connected to the same source terminal 8 remains at V.sub.L through other gate terminals 7, signal outputs from other pixels are not sensed.
Furthermore, the resetting operation which resets the pixels by clearing the accumulated signal charges and prepares the pixels for next signal accumulation is performed by changing the gate voltage applied to the gate electrodes 4 to a voltage V.sub.H so that a potential gradient which monotonically decreases in the depth-direction is provided. The signal charge (positive holes in this case) accumulated at the interface of the n-type well 2 and the insulating film 3 is discharged to the p-type substrate 1 side immediately below as illustrated by the broken lines in FIG. 1B.
In the above-described conventional CMD type pixels, if the impurity concentration of the buried channel layer which functions as the n-type well 2 is raised in order to increase the signal charge accumulation density, then the gate voltage V.sub.H during the above-described resetting operation must be set extremely high.
For example, the gate voltage V.sub.H during the resetting operation will be considered under the following conditions (condition 1).
(Condition 1)
Concentration in substrate: 1.0.times.10.sup.15 cm.sup.-3 PA0 Concentration in n-type layer: 3.0.times.10.sup.15 cm.sup.-3 PA0 Thickness of n-type layer: 1.5 .mu.m PA0 Thickness of gate insulating film: 80 nm
Under Condition 1, the critical condition for the potential to be monotonically decreasing from the surface of the n-type well 2 to the p-type substrate 1 is given by the following equation (1). ##EQU1## where N.sub.n denotes carrier concentration of the n-type well 2, N.sub.p denotes carrier concentration of the p-type substrate 1, K.sub.s denotes a dielectric constant of the substrate 1, .epsilon..sub.o denotes the permittivity in vacuum, q denotes the elementary electric charge, and D.sub.n denotes a junction depth X.sub.j of the n-type well 2.
Therefore, in the case where the flat band voltage is V.sub.FB =-0.85 V, the gate voltage V.sub.H required for the resetting operation is calculated to be V.sub.H =20.0 V from Equation (1), which is unpractically high.
Furthermore, other problems experienced by the conventional CMD type pixels include a large quantity of dark current due to the depletion at the interface between the n-type well 2 and the insulating film 3 when surrounding environment is dark.
In order to reduce the dark current in the FET type amplifying type solid-state imaging apparatus, an FGA type amplifying type solid-state imaging apparatus is proposed.
FIG. 3A is a cross-sectional view of a pixel of a conventional FGA type amplifying type solid-state imaging apparatus, and FIG. 3B shows the potential distribution in the depth-direction taken along the line K--K in FIG. 3A. This conventional technique is reported in "A New Device Architecture Suitable for High-Resolution and High-Performance Image Sensor", by J. Hynecek, IEEE Trans. Elec. Dev., p 646, (1988). In FIG. 3A, elements having similar functions as in FIG. 1A are designated by the same reference numerals and the descriptions thereof are omitted.
This FGA type device differs from the CMD type device in that a p.sup.+ -type layer 10 having relatively high impurity concentration is provided in a region of the n-type well 2 under the gate electrode 4 as illustrated in FIG. 3A.
In the FGA type amplifying type solid-state imaging apparatus having the above structure, the gate voltage is set at a voltage V.sub.L during the accumulation and read-out of a signal as illustrated in FIG. 3B. Then, a change in the channel potential in the n-type well 2 due to the accumulation of a signal charge (positive hole) in the p.sup.+ layer 10 is read out as a change in the threshold value. Other pixels connected to the same signal line are not read out since the gate voltage applied to these pixels is not V.sub.L.
Following the read-out operation, the resetting operation is similar to that of the above-described CMD type device. By changing the gate voltage to a voltage V.sub.H when resetting so as to provide a potential gradient which is monotonically decreasing in the depth-direction, the signal charge (positive hole) accumulated in the p.sup.+ -type layer is discharged to the p-type substrate 1 side directly below. Since this p.sup.+ -type layer 10 does not become depleted during the resetting operation, the dark current can be prevented. However, the fact that the p.sup.+ -type layer 10 does not become depleted also means that the signal charge is not completely transferred. This causes generation of an after image and an increase in the resetting noise.
In order to further improve the FGA type amplifying type solid-state imaging apparatus, a BCMD type amplifying type solid-state imaging apparatus has been proposed ("BCMD-An Improved Photosite Structure for High Density Image Sensor" by J. Hynecek, IEEE trans. Elec. Dev., p 1011, (1991)).
FIG. 4A is a cross-sectional view of a pixel of a conventional BCMD type amplifying type solid-state imaging apparatus, and FIG. 4B is a potential distribution in the depth-direction taken along the sectioning line L--L in FIG. 4A.
In FIG. 4A, the pixel of the BCMD type device includes a p-type layer 12, an n-type layer 13 and another p-type layer 14 successively deposited in this order on an n-type substrate 11. Then, a high impurity concentration p.sup.+ -type layer 15 which is intended for the source and the drain extending through the p-type layer 12, the n-type layer 13 and the p-type layer 14 is formed.
Comparing to the pixel of the above-described FGA type device, the pixel of the BCMD type device differs in that the signal charges are electrons accumulated in the n-type layer 13 functioning as the buried channel, that a potential change in the p-type layer 14 at the surface due to the signal charge is sensed as a change in the threshold value of P-MOS, and that the substrate 11 is an n-type and the gate voltage is set at a low voltage V.sub.L during the resetting operation so that the signal charge is discharged to the n-type substrate 11 side.
In this manner, a complete transfer of the signal charge is achieved. However, this structure requires the p-n-p-n multi-layer structure. As a result, the optimization of driving conditions becomes difficult to achieve, and its fabrication also becomes too complicated.
In order to solve those problems associated with each of the above-described amplifying type solid-state imaging apparatuses, the applicant of the present invention proposed four kinds of new structures to be described below, and separately filed the inventions in Japanese Patent Application Nos. 6-30953, 7-51641, 8-19199 and 8-19200, respectively.
FIG. 5 is a cross-sectional view of a pixel having a so-called TGMIS (Twin Gate MOS Image Sensor) type structure disclosed in Japanese Patent Application 6-30953. In the figure, an n-type well layer 62 is provided to the surface side of a p-type semiconductor substrate 61, and a source region 50 and a drain region 45 of the MOS-FET are provided to the surface side of the n-type layer 62. Furthermore, a first gate (photo gate) electrode 46 is provided on the n-type layer 62 with an insulating film 63 being inserted therebetween, and a second gate (resetting gate) electrode 48 is provided on the p-type semiconductor substrate 61 also with the insulating film 63 being inserted therebetween.
The first gate electrode 46 is connected to a control voltage terminal to which a read-out scanning voltage V.sub.A is applied. The source region 50 of the MOS-FET including the first gate electrode 46 as a gate is connected to a source terminal through which a pixel signal voltage V.sub.S read out from the pixel is obtained, and the drain region 45 of each pixel is connected to a drain terminal to which a drain voltage V.sub.D is applied.
Hereinafter, the operation of the above-described structure will be described.
First, a photon having optical energy h.nu. entering through the first gate electrode 46 creates an electron-hole pair due to photoelectric conversion, and the electron thus created flows into the drain region 45. The positive hole is confined by the potential barrier formed in the middle portion of the n-type layer 62 and by the potential barrier formed under the second gate electrode 48. The positive holes accumulate at the interface of the n-type layer 62 between the semiconductor and the insulating film as a signal charge.
A change in the potential within the n-type layer 62 in accordance with the signal charge can be read out as a voltage change in the source region 50, regarding it as an output signal of the pixel voltage.
The discharge of the signal charge is readily performed by lowering the potential barrier under the second gate electrode 48. The signal charge then flows to the p-type semiconductor substrate 61 side through the path indicated by the broken line in FIG. 5.
For example, in the structure where the signal charge is extracted directly to the substrate side as for the conventional CMD type, sufficient resetting cannot be performed unless relatively high voltage (10 V, for example) is applied to the first gate electrode. Moreover, if the impurity concentration in the n-type well layer is made small, a sufficient amount of charge cannot be accumulated. If the impurity concentration in the n-type well layer is made large, then a sufficient amount of accumulated charge can be obtained but, on the other hand, sufficient resetting cannot be performed unless high voltage (20 V, for example) is applied to the resetting gate. However, in the structure where the signal charge to be reset is first extracted in the horizontal direction and then to the substrate side as illustrated in FIG. 5, since the n-type well having the high impurity concentration can be used and a sufficient amount of the signal charge can be accumulated at the surface, a signal charge amount of sufficiently large magnitude can be handled and, at the same time, the resetting operation can be performed at lower voltage.
However, a problem still remains which is common to all currently known amplifying type solid-state imaging apparatuses, and the problem is associated with a fixed pattern noise (FPN) arising from the fluctuation of signal levels and amplification factors among pixels. Hereinafter, this problem associated with FPN will be described in detail with reference to the above-described TGMIS type amplifying type solid-state imaging apparatus as an example.
FIG. 6 schematically illustrates the structure of a two-dimensional amplifying-type solid-state imaging apparatus utilizing TGMIS type amplifying type solid-state imaging devices. A predetermined DC voltage V.sub.D is applied to a common drain 25 of each pixel such as pixels 21, 22, 23 and 24. First gate electrodes 26 of pixels arranged in the horizontal direction, such as pixels 21 and 22, are all connected to a first scanning line 26a placed in the horizontal direction so that a read-out operation is performed by a first vertical scanning circuit 27 via the first scanning line 26a. Second gate electrodes 28 of the same pixels as above arranged in the horizontal direction, such as pixels 21 and 22, are all connected to a second scanning line 28a placed in the horizontal direction so that a resetting operation is performed by a second vertical scanning circuit 29 via the second scanning line 28a in units of the horizontally-arranged pixels. Furthermore, source electrodes 30 of pixels arranged in the vertical direction, such as pixels 21 and 23 or pixels 22 and 24, are all connected to a signal line 31 in units of such pixels, and further connected to a video line 34 via a switching transistor 33 whose ons and offs are controlled by a horizontal scanning circuit 32. Furthermore, an MOS transistor 36 which provides a constant current load is connected to the output terminal 35 of the video line 34. This completes the construction of the two-dimensional amplifying type solid-state imaging apparatus utilizing the TGMIS type amplifying type solid-state imaging devices.
FIG. 7A is a timing chart for driving the two-dimensional amplifying type solid-state imaging apparatus in FIG. 6, and FIG. 7B is a structural diagram of its output signal.
In FIG. 7A, the scanning signal .phi.GI(i) is a control clock signal which is successively output from the first vertical scanning circuit 27 to the i-th group from the top of the first gate electrodes 26 of pixels arranged in the horizontal direction, and the scanning signal .phi.GII(i) is a control clock signal which is successively output from the second vertical scanning circuit 29 to the i-th group from the top of the second gate electrodes 28 of pixels arranged in the horizontal direction. For example, the scanning signal .phi.GI(1) from the first vertical scanning circuit 27 is input to the first gate electrodes 26 of pixels arranged in the horizontal direction such as pixels 21 and 22 so that read-out operation from pixels such as pixels 21 and 22 is selected.
Then, if the first gate electrodes 26 and the second gate electrodes 28 of the i-th group of horizontally arranged pixels from the top are at high levels VG(H) and VRG(H), respectively, while the first gate electrodes 26 and the second gate electrodes 28 of other pixels are all at low levels VG(L) and VRG(L), respectively, then only the pixel signals stored in the i-th group of horizontally arranged pixels from the top can be read out to the signal lines 31. The clock pulses .phi.S1, .phi.S2, .phi.S3, etc. which are output from the horizontal scanning circuit 32 during the period (.tau.H) successively select the signal line 31 placed in the vertical direction by controlling ons and offs of the switching transistors 33. Then, the pixel signals from the i-th group of vertically arranged pixels from the left are output to the video line 34 as output signals via the signal line 31 and the switching transistor 33.
Then, during the period (.tau.BL) in which the first gate electrodes 26 of the i-th group of horizontally arranged pixels from the top are at high level VG(H) but the second gate electrodes 28 of the same group of pixels are at low level VRG(L), the resetting operation is performed by the second vertical scanning circuit 29 in units of pixels arranged in the horizontal direction.
As illustrated in FIG. 7B, the signal output waveform of the pixel signal obtained by the clock pulses .phi.S1, .phi.S2, .phi.S3, etc. also includes a fluctuation component of an output voltage when there is no optical input (photoelectrically generated and accumulated charge is zero) to the pixels of the amplifying type solid-state imaging devices which are successively selected. As a result, it is not possible to obtain only the signal amount of the output signal due to the net amount of photoelectrically generated and accumulated charge, posing a problem associated with a fixed pattern noise arising from the fluctuation of signal level and amplification factor of each pixel.